1. Field of the Invention
This invention relates to high density circuit packages, and more particularly to three-dimensional circuit assemblies and fabrication techniques for packaging either multiple integrated circuit layers as a unitary assembly, or a focal plane array together with associated readout circuitry.
2. Description of the Related Art
In an attempt to increase the density of integrated circuit (IC) packages, efforts have been made to incorporate multiple circuit layers within the same package, with various mechanisms for interconnecting the different layers and providing externally accessible input/output ports. In a similar vein, effort has also been directed towards integrating the fabrication of a focal plane array with its readout circuitry.
One of the challenges in successfully implementing a 3-D circuit package has been to bring connections for the interior circuit layers out to the exterior of the package so they can be readily addressed by the user. One method to accomplish this has been developed by Hughes Aircraft Company, the assignee of the present invention, and is referred to as the thermal gradient zone melt technique. This approach is described in M. J. Little et al., "The 3-D Computer", Proc. of IEEE Int'l. Conf. on Wafer Scale Integration, Jan. 3, 1989, pages 55-64. It involves the distribution of aluminum dots on the surface of a silicon wafer within which circuit layers have been fabricated. A device is heated to about 1,100.degree.-1,200.degree. C., causing the aluminum dots to melt and dissolve into the underlying silicon. This produces a conductive feedthrough composed of an aluminum/silicon alloy extending into the wafer from the location of each dot, and having a much lower resistivity than the surrounding silicon. The feedthroughs extend down to the circuit layer and thereby provide an external electrical access. While successfully producing feedthroughs to the circuit layers, this technique is subject to density limitations in the zone melts, and can result in a feedthrough capacitance that is excessive for certain applications.
In the area of focal plane arrays, a "loop hole" or "VIMIS" (vertically integrated metal-insulator-semiconductor) technique has been developed in which a chip of photodetector material is glued to readout circuitry. The photodetector is then thinned, and openings are etched through it to access contact pads for an integrated circuit on the other side of the chip. The openings are then metallized to provide electrical connections through the detector to the readout circuitry. This technique is described, for example, in Amingual, "Advanced Infrared Multiple Plane Arrays", SPIE Infrared and Optoelectronic Materials and Devices, Vol. 1512, 1991, pages 40-51. However, it is limited to n on p detectors and has a fill factor limitation, meaning that the etched openings through the photodetector reduce the amount of material left to perform the photodetection function. Since the detector substrate must be relatively thick, the etched openings expand to undesirably large dimensions towards the surface of the photodetector.
Another focal plane array assembly uses indium "bumps" to mechanically secure a detector chip to a cell processing chip, and to provide a matrix of electrical contacts therebetween. This technique is described in U.S. Pat. No. 4,740,700, assigned to Hughes Aircraft Company, and is also referred to in the Amingual reference mentioned above. Although the bumps establish interconnects between two interior layers of the overall device, they do not provide access to the readout circuitry from an exterior surface of the device.